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TMP86FS49AIUG Folha de dados(PDF) 87 Page - Toshiba Semiconductor

Nome de Peças TMP86FS49AIUG
Descrição Electrónicos  8 Bit Microcontroller
PDF  296 Pages
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Fabricante Electrônico  TOSHIBA [Toshiba Semiconductor]
Página de início  http://www.semicon.toshiba.co.jp/eng
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TMP86FS49AIUG Folha de dados(HTML) 87 Page - Toshiba Semiconductor

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TMP86FS49AIUG
6.3.4
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum
24/fc [s] (1.5
µs @ fc = 16.0 MHz).
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.



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