All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

control bits permit software to control the

edge(s) that trigger each input-capture func-

tion and the automatic actions that result from

output-compare functions. Although hardwired

logic is included to automate many timer ac-

tivities, this timer architecture is essentially a

software-oriented system. This structure is

easily adaptable to a very wide range of appli-

cations although it is not as efficient as dedi-

cated hardware for some specific timing appli-

cations.

Watchdog Timer -

The Watchdog Timer con-

trol logic. The Watchdog Timer can be en-

abled by software by writing ‘1’ to the WDOG

bit in MISC register($000C). Once enabled

the WDT Timer cannot be disabled by soft-

ware. In addition the WDOG bit acts as a re-

set mechanism for the WDT timer. Writing

logic one ‘1’ to the WDOG bit clears Watch-

dog counter and inhibits Watchdog timeout

SCI

- The SCI is a full-duplex UART type

asynchronous system, using standard non

return to zero (NRZ) format : 1 start bit, 8 or 9

data bits and a 1 stop bit. The DF6808 resyn-

chronizes the receiver bit clock on all one to

zero transitions in the bit stream. Therefore

differences in baud rate between the sending

device and the SCI are not as likely to cause

reception errors. Three logic samples are

taken near the middle of data bit time, and

majority logic decides the sense for the bit.

For the start and stop bits seven logic sam-

ples are taken. Even if noise causes one of

these samples to be incorrect, the bit will still

be received correctly. The receiver also has

the ability to enter a temporary standby mode

(called receiver wakeup) to ignore messages

intended for a different receiver. Logic auto-

matically wakes up the receiver in time to see

the first character of the next message. This

wakeup feature greatly reduces CPU over-

head in multi-drop SCI networks. The SCI

transmitter can produce queued characters of

idle (whole characters of all logic 1) and break

(whole characters of all logic 0). In addition to

the usual transmit data register empty (TDRE)

status flag, this SCI also provides a transmit

complete (TC) indication that can be used in

applications with a modem.

SPI Unit

– it’s a fully configurable mas-

ter/slave Serial Peripheral Interface, which

allows user to configure polarity and phase of

serial clock signal SCK. It allows the micro-

controller to communicate with serial periph-

eral devices. It is also capable of interproces-

sor communications in a multi-master system.

A serial clock line (SCK) synchronizes shifting

and sampling of the information on the two

independent serial data lines. SPI data are

simultaneously transmitted and received. SPI

system is flexible enough to interface directly

with numerous standard product peripherals

from several manufacturers. Data rates as

high as CLK/4. Clock control logic allows a

selection of clock polarity and a choice of two

fundamentally different clocking protocols to

accommodate most available synchronous

serial peripheral devices. When the SPI is

configured as a master, software selects one

of four different bit rates for the serial clock.

SPI automatically drives slave select outputs

SSO[7:0], and address SPI slave device to

exchange serially shifted data. Error-detection

logic is included to support interprocessor

communications. A write-collision detector

indicates when an attempt is made to write

data to the serial shift register while a transfer

is in progress. A multiple-master mode-fault

detector automatically disables SPI output

drivers if more than one SPI devices simulta-

neously attempts to become bus master.

DoCD

ware debugger provides debugging capability

of a whole SoC system. In contrast to other

on-chip debuggers DoCD™ provides non-

intrusive debugging of running application. It

can halt, run, step into or skip an instruction,

read/write any contents of microcontroller in-

cluding all registers, internal, external, pro-

gram memories, all SFRs including user de-

fined peripherals. Hardware breakpoints can

be set and controlled on program memory,

internal and external data memories, as well

as on SFRs. Hardware breakpoint is executed

if any write/read occurred at particular address

with certain data pattern or without pattern.

face and complete set of tools to communi-

cate and work with core in real time debug-

ging. It is built as scalable unit and some fea-

tures can be turned off to save silicon and

reduce power consumption. A special care on

power consumption has been taken, and

when debugger is not used it is automatically

switched in power save mode. Finally whole

debugger is turned off when debug option is

no longer used.