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TMP93CS32F Folha de dados(PDF) 28 Page - Toshiba Semiconductor

Nome de Peças TMP93CS32F
Descrição Electrónicos  CMOS 16-Bit Microcontroller
PDF  180 Pages
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Fabricante Electrônico  TOSHIBA [Toshiba Semiconductor]
Página de início  http://www.semicon.toshiba.co.jp/eng
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TMP93CS32F Folha de dados(HTML) 28 Page - Toshiba Semiconductor

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TMP93CS32
2004-02-10
93CS32-26
Resetting initializes the CPU mask registers <IFF2:0> to 7; therefore, maskable
interrupts are disabled.
The following (1) to (5) show a flowchart of interrupt processing.
(1) Maskable
(2) Non-maskable interrupt
(3) Interrupt nesting
(4) Software interrupt
(5) Interrupt sampling timing
During execution of the main program, the CPU
accepts an interrupt request. The CPU increments the
IFF so that the interrupts of level 1 are not accepted
during processing the interrupt routine.
(Main)
DI
[4]
[2]
[3]
RETI
[1]
SWI3
[5]
The CPU accepts the software interrupt request
during DI status(IFF
= 7) because of the level 7. The
IFF is not changed by the software interrupts.
(SWI3 routine)
Example:
(Underline): Instruction
[1], [2] …: Execution flow
RETI
(Main)
EI 3
[7]
[6]
RETI
[1]
INTT0
(Level 3)
[8]
If an interrupt with a level higher than the interrupt being
processed is generated, the CPU accepts the interrupt with the
higher level. The program counter which returns at e is the start
address of INTT0 interrupt routine.
(INTT0 interrupt routine)
XXX
INTT1
(Level 4)
[2]
[4]
RETI
[3]
[5]
(Main)
EI 3
[8]
[2]
[7]
RETI
[1]
INTT0
(Level 3)
[9]
During processing the interrupts of level 3, the IFF is set to 4.
When an interrupt with a level higher than level 4 is generated,
the CPU accepts the interrupt with the higher level, causing
interrupt processing to nest.
(INTT0 interrupt routine) (INTT1 interrupt routine)
IFF
← 4
IFF
← 3
[3]
INTT1
(Level 4)
[6]
[4]
[5]
IFF
← 5
IFF
← 4
(Main)
EI 1
[4]
[2]
[3]
RETI
[1]
INTT0
(Level 1)
[5]
(INTT0 interrupt routine)
IFF
← 2
IFF
← 1
(Main)
DI
[4]
[2]
[3]
RETI
[1]
NMI
(Level 7)
[5]
DI instruction is executed in the main program, so that
the interrupts of only level 7 are accepted. The CPU
does not increment the IFF even if the CPU accepts
an interrupt request of level 7.
(NMI interrupt routine)
IFF
← 7
IFF
← 7



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