STM32H562VG datasheet(52/270 Pages) STMICROELECTRONICS

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Functional overview

STM32H562xx and STM32H563xx

52/270

DS14258 Rev 5

3.36

Improved inter-integrated circuit (I3C)

The I3C interface handles communication between the MCU and others, like sensors and

host processor(s), all connected on an I3C bus.

The peripheral implements the required features of the MIPI I3C specification v1.1. It can

control I3C bus-specific sequencing, protocol, arbitration and timing, and can act as

controller (formerly known as master) or as target (formerly known as slave). When acting

as controller the peripheral improves the features of the I2C interface, preserving some

backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C

fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does not

perform clock stretching.

The I3C peripheral can be used with DMA to off-load the CPU.

Table 8. I3C peripheral controller/target features versus MIPI v1.1

Feature

MIPI

v1.1

When

controller

When

target

Comments

I3C SDR message

Legacy I2C message (Fm/Fm+)

Mandatory when controller, and the I3C bus is

mixed with (external) legacy I2C target(s).

Optional in MIPI v1.1 when target.

HDR DDR message

Optional in MIPI v1.1

HDR-TSL/TSP, HDR-BT

Dynamic address assignment

Static address

No (intended) support of I3C peripheral as a

target on an I2C bus.

Grouped addressing

Optional in MIPI v1.1

CCCs

Mandatory and some optional CCCs supported.

Error detection and recovery

In-band interrupt (with MDB)

Secondary controller

Hot-join mechanism

Target reset

Synchronous timing control

Optional in MIPI v1.1

Asynchronous timing control 0

Asynchronous timing control 1, 2, 3

Device to device tunneling

Multi-lane data transfer

Monitoring device early termination

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