d 

High Speed CMOS Logic – 54HC112

 

 

Rev 1.0

24/11/17

Pad Layout and Functions

 

 

  

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1500µm (59.06 mils)

COORDINATES (mm)

PAD

FUNCTION

0,0

X

Y

1

1CLK

0.125

0.345

2

1K

0.135

0.125

3

1J

0.585

0.135

4

1PRE

0.755

0.135

5

1Q

1.025

0.135

6

1Q

1.225

0.135

7

2Q

1.245

0.54

8

GND

1.245

0.735

9

2Q

1.26

0.995

10

2PRE

1.26

1.165

11

2J

1.25

1.47

12

2K

0.86

1.48

13

2CLK

0.48

1.48

14

2CLR

0.125

1.47

15

1CLR

0.125

0.855

16

VCC

0.125

0.615

CONNECT CHIP BACK TO VCC OR FLOAT

9

8

7

6

5

4

3

2

1

16

15

14

13

12

10

11

DIE ID

Truth Table

Logic Diagram

INPUTS

OUTPUTS

PRE

CLR

CLK

J

K

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H*

H*

H

H

↓

L

L

NO CHANGE

H

H

↓

H

L

H

L

H

H

↓

L

H

L

H

H

H

↓

H

H

TOGGLE

H

H

H

X

X

NO CHANGE

H = High level (steady state), L = Low level (steady state)

X = Don’t care, ↓ = High-to-Low transition

* Output states unpredictable if both PRE and CLR go High

simultaneously after both being low at the same time.

x1 Flip-Flop

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