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ELANSC310 Folha de dados(PDF) 43 Page - Advanced Micro Devices |
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ELANSC310 Folha de dados(HTML) 43 Page - Advanced Micro Devices |
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43 / 119 page ![]() Élan™SC310 Microcontroller Data Sheet 43 PREL IMINARY (ISA Cycle) + (DMA Cycle) + (Low Speed) 2 x CPU Clock High Speed PLL (I4) 18.432 MHz Programmable Low Speed (I0–I3) Divide Chain 18.432 9.216 4.608 2.304 1.152 I4 I3 I2 I1 I0 S2 Internal SYSCLK DMA Clock External SYSCLK 0 1 ÷ 2 ÷ 4 ÷ 2 2 x CPU/Local Bus Clock S[1:0] Figure 2. Clock Steering Block Diagram (Low-Speed PLL mode only) |
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