ML145151 datasheet(18/35 Pages) LANSDALE

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Issue A

LANSDALE Semiconductor, Inc.

ML145157

14–BIT SHIFT REGISTER

14–BIT

÷ N COUNTER

φV

ML145157 BLOCK DIAGRAM

φR

REFERENCE COUNTER LATCH

PHASE

DETECTOR

PHASE

DETECTOR

LOCK

DETECT

PDout

fin

OSCin

OSCout

ENB

14–BIT SHIFT REGISTER

DATA

CLK

REFout

÷ N COUNTER LATCH

14–BIT

÷ R COUNTER

S/Rout

1–BIT

CONTROL

S/R

PIN DESCRIPTIONS

INPUT PINS

fin

Frequency Input (Pin 8)

Input frequency from VCO output. A rising edge signal on

this input decrements the ÷ N counter. This input has an invert-

er biased in the linear region to allow use with AC coupled sig-

nals as low as 500 mV p–p. For larger amplitude signals (stan-

dard CMOS logic levels), DC coupling may be used.

CLK, DATA

Shift Clock, Serial Data Inputs (Pins 9, 10)

Each low–to–high transition of the clock shifts one bit of

data into the on–chip shift registers. The last data bit entered

determines which counter storage latch is activated; a logic

1selects the reference counter latch and a logic 0 selects the

÷ N counter latch. The entry format is as follows:

ENB

Latch Enable Input (Pin 11)

A logic high on this pin latches the data from the shift regis-

ter into the reference divider or ÷ N latches depending on the

control bit. The reference divider latches are activated if the

control bit is at a logic high and the ÷ N latches are activated if

the control bit is at a logic low. A logic low on this pin allows

the user to change the data in the shift registers without affect-

ing the counters. ENB is normally low and is pulsed high to

transfer data to the latches.

OSCin, OSCout

Reference Oscillator Input/Output (Pins 1, 2)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

nected from OSCin to ground and OSCout to ground. OSCin

may also serve as the input for an externally–generated refer-

ence signal. This signal is typically AC coupled to OSCin, but

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

connection is required to OSCout.

OUTPUT PINS

PDout

Single–Ended Phase Detector A Output (Pin 5)

This single–ended (three–state) phase detector output pro-

duces a loop–error signal that is used with a loop filter to con-

trol a VCO.

Frequency fV > fR or fV Leading: Negative Pulses

Frequency fV < fR or fV Lagging: Positive Pulses

Frequency fV = fR and Phase Coincidence:

High–Impedance State

φR, φV

Double–Ended Phase Detector B Outputs (Pins 16, 15)

These outputs can be combined externally for a loop–error

signal. A single–ended output is also available for this purpose

(see PDout).

FIRST DATA BIT INTO SHIFT REGISTER

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