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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AS8267 Folha de dados(PDF) 67 Page - ams AG |
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AS8267 Folha de dados(HTML) 67 Page - ams AG |
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67 / 136 page  Data Sheet AS8267 / AS8268 Revision 1.0, 19-Jun-07 Page 67 of 136 8.5 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) represents a synchronous, bit serial 4-wire interface for full-duplex data transfer. Depending on the operating mode (selectable by the sel_spi2 bit in the SCT enable signals register (9001h)) the interface can act as SPI2 Master/Slave interface (e.g. when an external EEPROM is connected) or as SPI_FLASH interface (when used as interface to the Flash). SPI Interface SPI_FLASH sel_spi2 =0 Master Mode Slave Mode SPI2 sel_spi2 =1 Figure 8: SPI Interface 8.5.1. SPI2 Master/Slave Mode In this mode the SPI can operate in master mode, whereas the external EEPROM works in slave mode. The external EEPROM memory must fulfil the requirements described below. The EEPROM is selectable in size from 1kByte to 32kByte in binary steps. Key Features - Standard 4 wire synchronous serial interface (MISO, MOSI, SC, S_N) - Master/slave mode operation - 8-bit word length (variable transmit/receive word optional) - Shift clock SC high when idle - MSB is always transmitted first - Four selectable clocking schemes (clock idle state / clock phase) - Selectable SPI clock rate divider (from mcu_clk/2 to mcu_clk/65536) - Three maskable interrupts (transmission complete, overrun, collision) |
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