HT82A850R datasheet(6/41 Pages) HOLTEK

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HT82A850R

Rev. 1.10

July 25, 2007

Functional Description

Execution Flow

The microcontroller system clock is sourced from a crys-

tal oscillator. The system clock is internally divided into

four non-overlapping clocks. One instruction cycle con-

sists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to be effectively executed in a cycle. If an instruction

changes the program counter, two cycles are required to

complete the instruction.

Program Counter

- PC

The program counter, PC, controls the sequence in

which the instructions stored in the program memory are

executed. Its contents specify the full program memory

range.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

When executing a jump instruction, a conditional skip

execution, loading to the PCL register, performing a

subroutine call or returning from a subroutine, an initial

reset, an internal interrupt, external interrupt or return

from interrupts, the PC manipulates the program trans-

fer by loading the address corresponding to each in-

struction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise the next instruction is executed.

The lower byte of the program counter, PCL, is a read-

able and writeable register. Moving data into the PCL

performs a short jump. The destination will be within the

current program memory page.

When a control transfer takes place, an additional

dummy cycle is required.

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

Execution Flow

Mode

Program Counter

*11

*10

Initial Reset

000000000000

Reserved

000000000100

Timer/Event Counter 0 Overflow

000000001000

Timer/Event Counter 1 Overflow

000000001100

Play Interrupt

000000010000

Serial Interface Interrupt

000000010100

Record Interrupt

000000011000

Skip

Program Counter+2

Loading PCL

*11

*10

Jump, Call Branch

#11

#10

Return from Subroutine

S11

S10

Program Counter

Note: *11~*0: Program counter bits

S11~S0: Stack register bits

#11~#0: Instruction code bits

@7~@0: PCL bits

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