HT82A822R

Rev. 1.10

21

June 29, 2007

DAC_Limit_L and DAC_Limit_H are used to define the 16-bit DAC output limit. DAC_Limit_L and DAC_Limit_H are un-

signed value. If the 16-bit data from Host over the range defined by DAC_Limit_L and DAC_Limit_H, the output digital

code to DAC will be clamp.

DAC_Limit_L

DAC output limit low byte

DAC_Limit_H

DAC output limit high byte

Setting DAC output limit value example:

;-----------------------------------------------------------

; DAC Limit POR Value=8000H

; Set DAC Limit Value=FF00H

;-----------------------------------------------------------

clr

[02DH]

; Set DAC Limit low byte=00H

set

[02EH]

; Set DAC Limit high byte=FFH

;-----------------------------------------------------------

In order to prevent the pop noise of speaker output, power amplifier should be output at the value of VDD/2 (send

8000H to DAC) during the initial power on state. If software set high then clear the bit DAC_WR_TRIG (bit 3 of

DAC_WR register), the value on the DAC_Limit_L and DAC_Limit_H registers will write to DAC.

Bit No.

Label

R/W

Power-on

Functions

0~2, 4~7

¾

R0

Undefined bit, read as

²0².

3

DAC_WR_TRIG

R/W

0

DAC write trigger bit

DAC_WR (2FH) Register

Example to avoid popping noise:

System_Initial:

;-----------------------------------------------------------

; Avoid Pop Noise

;-----------------------------------------------------------

mov

a,WDTS

mov

FIFO_TEMP,a

;Save WDTS value

mov

a,01010000b

andm

a,WDTS

mov

a,01010000b

orm

a,WDTS

;Enter DAC Write Data mode, high nibble of WDTS=0101b

clr

[02DH]

;Set DAC data low byte=00H

mov

a,80H

mov

[02EH],a

;Set DAC data high byte=80H

nop

;Write 8000H to DAC

set

[02FH].3

nop

clr

[02FH].3

nop

;-----------------------------------------------------------

mov

a,FIFO_TEMP

;Restore WDTS value

mov

WDTS,a

;Quit DAC Write Data mode

;-----------------------------------------------------------

Note: At DAC write data mode (high nibble of WDTS register is 0101b), DAC_Limit_L and DAC_Limit_H registers will

be the 16-bit DAC input data register at falling edge of DAC_WR_TRIG. Otherwise, these two registers are

used to define the 16-bit DAC output limit.