405GPR datasheet(8/57 Pages) AMCC

8 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

DCR Address Map 4KB Device Configuration Registers

Function

Start Address

End Address

Size

Total DCR Address Space1

0x000

0x3FF

1KW (4KB)1

By function:

Reserved

0x000

0x00F

16W

Memory Controller Registers

0x010

0x011

External Bus Controller Registers

0x012

0x013

Decompression Controller Registers

0x014

0x015

Reserved

0x016

0x017

On-Chip Memory Controller Registers

0x018

0x01F

Reserved

0x020

0x07F

96W

PLB Registers

0x080

0x08F

16W

Reserved

0x090

0x09F

16W

OPB Bridge Out Registers

0x0A0

0x0A7

Electronic Chip ID (ECID)

0x0A8

0x0A9

Reserved

0x0AA

0x0AF

Clock, Control, Interrupt Routing, and Reset

0x0B0

0x0B7

Power Management

0x0B8

0x0BF

Interrupt Controller

0x0C0

0x0CF

16W

Reserved

0x0D0

0x0FF

48W

DMA Controller Registers

0x100

0x13F

64W

Reserved

0x140

0x17F

64W

Ethernet MAL Registers

0x180

0x1FF

128W

Reserved

0x200

0x3FF

512W

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register, or 1 kiloword (KW) (which equals 4 KB).

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