PPC405EP datasheet(47/50 Pages) AMCC

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PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

Data Sheet

Table 15. I/O Specifications—Group 2

Notes:

1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM.

2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.

3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS

model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

5. IOH is specified at 2.4V and IOL is specified at 0.4V.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

IOH

(minimum)

IOL

(minimum)

SDRAM Interface

BA1:0

4.7

15.3

10.2

MemClkOut

1, 2

BankSel3:0

4.5

1.7

15.3

10.2

MemClkOut

1, 2

CAS

4.8

15.3

10.2

MemClkOut

1, 2

ClkEn0:1

4.1

1.6

28.7

19.3

MemClkOut

1, 2

DQM0:3

4.7

1.9

15.3

10.2

MemClkOut

1, 2

MemAddr12:00

4.8

2.1

15.3

10.2

MemClkOut

1, 2

MemData00:31

1.6

1.2

15.3

10.2

MemClkOut

1, 2

RAS

2.1

15.3

10.2

MemClkOut

1, 2

4.9

15.3

10.2

MemClkOut

1, 2

External Slave Peripheral Interface

PerAddr06:31

3.8

1.6

15.3

10.2

PerClk

[PerBLast]4

PerClk

PerCS0

[PerCS1:4]

4.1

1.5

10.3

7.1

PerClk

PerData00:31

6.4

1.5

15.3

10.2

PerClk

PerOE

4.1

1.5

10.3

7.1

PerClk

PerR/W

4.1

1.6

10.3

7.1

PerClk

PerReady

6.5

PerClk

PerWBE0:3

4.1

1.6

10.3

7.1

PerClk

ExtReset

15.3

10.2

PerClk

0.4

-0.2

15.3

10.2

PLB Clk

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