NPE405H datasheet(7/70 Pages) AMCC

7 / 70 page

NPe405H – PowerNP NPe405H Embedded Processor

Revision 1.01 – April 18, 2007

AMCC Proprietary

DS2011

Data Sheet

ADDRESS MAP SUPPORT

The NPe405H incorporates two separate address maps. The first is a fixed processor address map that serves the

PowerPC family of processors. This address map defines the possible contents of various address regions which

the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are

accessed by software running on the NPe405H processor through the use of mtdcr and mfdcr commands.

SYSTEM ADDRESS MAP

Table 1. System Address Map 4GB Total System Memory

Function

Subfunction

Start Address

End Address

Size

General use

SDRAM, External peripherals, and PCI

memory

Note: Any of the address ranges listed at

right may be use for any of the above

functions.

0x00000000

0xE7FFFFFF

3712MB

0xE8010000

0xE87FFFFF

8MB

0xEC000000

0xEEBFFFFF

44MB

0xEEE00000

0xEF3FFFFF

6MB

0xEF500000

0xEF5FFFFF

1MB

0xEF900000

0xFFFFFFFF

263MB

Boot-up

External peripheral bus boot

0xFFE00000

0xFFFFFFFF

2MB

PCI boot

0xFFFE0000

0xFFFFFFFF

128KB

PCI

PCI I/O

0xE8000000

0xE800FFFF

64KB

PCI I/O

0xE8800000

0xEBFFFFFF

56MB

Configuration registers

0xEEC00000

0xEEC00007

Interrupt Acknowledge and special cycle

0xEED00000

0xEED00003

Local configuration registers

0xEF400000

0xEF40003F

64B

Internal peripherals

UART0

0xEF600300

0xEF600307

UART1

0xEF600400

0xEF600407

IIC0

0xEF600500

0xEF60051F

32B

OPB arbiter

0xEF600600

0xEF60063F

64B

GPIO0 controller registers

0xEF600700

0xEF60077F

128B

GPIO1 controller registers

0xEF600780

0xEF6007FF

128B

Ethernet MAC 0 registers

0xEF600800

0xEF6008FF

256B

Ethernet MAC 1 registers

0xEF600900

0xEF6009FF

256B

Ethernet MAC 2 registers

0xEF600A00

0xEF600AFF

256B

Ethernet MAC 3 registers

0xEF600B00

0xEF600BFF

256B

ZMII control registers

0xEF600C10

0xEF600C1F

16B

HDLCEX

0xEF610000

0xEF61FFFF

64KB

HDLCMP

0xEF620000

0xEF62FFFF

64KB

Notes:

1. When external peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.

2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.

3. After the boot process, software may reassign the boot memory regions for other uses.

4. All address ranges not listed above are reserved.

NPE405H Folha de dados(PDF) 7 Page - Applied Micro Circuits Corporation

NPE405H Folha de dados(HTML) 7 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Folha de dados Download

Ligação URL