Data Sheet

LT8349

analog.com

Rev B

23 of 29

Figure 31. Simplified Model for Loop Response

Board Layout

The LT8349 is specifically designed to minimize the electromagnetic interference (EMI) emissions and to maximize

efficiency when switching at high frequencies. Figure 32 shows a recommended PCB layout (simplified) for LT8349

(circuits connected SYNC, EN, and ISET are not shown). For more detail and PCB design files refer to the evaluation

board user guide for the LT8349.

To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC

is essential, especially the power paths with higher di/dt. Refer to Figure 32, the following high di/dt loops should be

kept as tight as possible to reduce inductive ringing and EMI emissions.



The high di/dt loop of channel 1 is formed by the positive terminal of COUT1, LT8349’s (C-G)1 pins, LT8349’s PGND

pins, and the negative terminal of COUT1.



The high di/dt loop of channel 2 is formed by the positive terminal of COUT2, LT8349’s (C-G)4 pins, LT8349’s PGND

pins, and the negative terminal of COUT2.

COUT

R1

C1

R2

CIN

RC

CC

CC2

1MΩ

L1

L2

CURRENT-MODE

POWER STAGE 1

VC

FB

VOUT

CURRENT-MODE

POWER STAGE 2

VC

INPUT

gm = 0.4mS

gm1 = 6S × (1 – D)

1V

VC

gm2 = 6S × (1 – D)

IOUT1

IOUT2

LT8349

IVC