TDA4VEN...Q1 datasheet(97/236 Pages) TI

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6.9.2.2.1 Power-Up Sequencing

Table 6-4 and Figure 6-5 describes the device power-up sequencing.

Note

The power supply sequencing requirements defined in this section does not include entry or exit

from low power modes. See the Partial IO Power Sequencing section for more information on the

requirements for entering or exiting from Partial IO low power mode.

Note

All power rails must be turned off and decay below 300mV before initiating a new power-up

sequence anytime a power rail drops below the minimum value defined in Recommended

Operating Conditions. The only exception is when entering/exiting Partial IO low power mode with

VDDSHV_CANUART and VDD_CANUART sourced from an always on power source. For this use

case the VDDSHV_CANUART and VDD_CANUART power rails are allowed to remain on.

Table 6-4. Power-Up Sequencing – Supply / Signal Assignments

See: Figure 6-5

WAVEFORM

SUPPLY / SIGNAL NAME

VSYS(1), VMON_VSYS(2)

VDDSHV_CANUART(3), VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDA_3P3_USB,

VMON_3P3_SOC(4)

VDDSHV_CANUART(5), VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDS_MMC0,

VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSI_DSI, VDDA_1P8_OLDI0,

VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1, VMON_1P8_SOC(6)

VDDSHV5(7), VDDSHV6(7)

VDDS_DDR(8), VDDS_DDR_C(8)

VDD_CANUART(9)

VDD_CANUART(10), VDD_CORE(10) (12), VDDA_CORE_CSI_DSI(10), VDDA_CORE_DSI_CLK(10),

VDDA_CORE_USB0(10), VDDA_DDR_PLL0(10)

VDD_CANUART(11), VDD_CORE(11) (12), VDDA_CORE_CSI_DSI(11), VDDA_CORE_DSI_CLK(11),

VDDA_CORE_USB0(11), VDDA_DDR_PLL0(11), VDDR_CORE(12), VDD_MMC0, VDDA_0P85_DLL_MMC0

VPP(13)

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

(1)

VSYS represents the name of a supply which sources power to the entire system. This supply is expected to be a pre-regulated supply

that sources power management devices which source all other supplies.

(2)

VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see the Section 8.2.4,

System Power Supply Monitor Design Guidelines.

(3)

VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V

depending on the application requirements.

VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any

valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power

source and is operating at 3.3V, it shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.

When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V

supplies during the 3.3V ramp period defined by this waveform.

(4)

The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected to the respective 3.3V supply source.

(5)

VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V

depending on the application requirements.

VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any

valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power

source and is operating at 1.8V, it shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.

When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V

supplies during the 1.8V ramp period defined by this waveform.

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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