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AS7C3513C Folha de dados(PDF) 2 Page - Alliance Semiconductor Corporation

Nome de Peças AS7C3513C
Descrição Electrónicos  3.3 V 32K X 16 CMOS SRAM
PDF  9 Pages
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Fabricante Electrônico  ALSC [Alliance Semiconductor Corporation]
Página de início  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C3513C Folha de dados(HTML) 2 Page - Alliance Semiconductor Corporation

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AS7C3513C
9/5/06, v 1.0
Alliance Memory
P. 2 of 9
®
Functional description
The AS7C3513C is a 3V high-performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as
32,768 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10 ns with output enable access times (tOE) of 5 ns are ideal for high-
performance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle
2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable
(OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. AS7C3513C is packaged in
common industry standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: H = high, L = low, X = don’t care.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+4.60
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–1.25
W
Storage temperature (plastic)
Tstg
–55
+125
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–50
mA
Truth table
CE
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
HXXXX
High Z
High Z
Standby (ISB), ISBI)
LH
L
L
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
LH
LH
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
H
LLL
DOUT
DOUT
Read I/O0–I/O15 (ICC)
LL
X
L
L
DIN
DIN
Write I/O0–I/O15 (ICC)
LL
X
L
H
DIN
High Z
Write I/O0–I/O7 (ICC)
LL
X
H
L
High Z
DIN
Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (ICC)



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