TUSB2E221 datasheet(28/65 Pages) TI

28 / 65 page

Note

Frame based low power mode is enabled by default. If using TUSB2E221 in pin-strap mode, this

feature can not be disabled. Contact support if a device variant with frame based low power mode

disabled in pin-strap mode is needed.

8.5 Programming

8.5.1 I2C Target Interface

I2C target interface enables access to internal registers by the system application processor. The primary

function of the interface is to enable configuring various PHY parameters, controlling the GPIO pins, and

enabling USB-BC functions. The TUSB2E221 repeater functions operates after power up without requiring I2C

configuration.

The TUSB2E221 has I2C 7-bit target address of 0x4F. 8-bit address of Write: 0x9E and Read: 0x9F.

I2C default target address can be changed at the factory through one-time programming.

I2C drive strength can be changed through the I2C.

Table 8-5. Recommended I2C Drive Strength for I2C Bus Speed, Bus Pullup and Bus Capacitance

I2C FM+ (1MHz Max)

I2C drive strength (IOL) selection

I2C bus pullup RPU

C(bus) pF

1kΩ

2.2kΩ

4kΩ

7kΩ

10-50

≅8mA

≅4mA

N/A

10-90

≅8mA

N/A

10-150

N/A

10-200

N/A

I2C FM (400kHz Max)

I2C drive strength (IOL) selection

I2C bus pullup RPU

C(bus) pF

1kΩ

2.2kΩ

4kΩ

7kΩ

10-50

≅8mA

≅4mA

≅2mA

N/A

10-90

≅8mA

≅4mA

N/A

10-150

≅8mA

N/A

10-200

≅8mA

N/A

I2C STD (100kHz Max)

I2C drive strength (IOL) selection

I2C bus pullup RPU

C(bus) pF

1kΩ

2.2kΩ

4kΩ

7kΩ

10-50

≅8mA

≅4mA

≅2mA

≅1mA

10-90

≅8mA

≅4mA

≅2mA

≅1mA

10-150

≅8mA

≅4mA

≅2mA

10-200

≅8mA

≅4mA

≅2mA

Figure 8-5. I2C Write with Data

Use this procedure to write data to TUSB2E221 I2C registers (refer to Figure 8-5):

TUSB2E221

SNLS757B – JUNE 2024 – REVISED NOVEMBER 2024

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