MCP8021 datasheet(22/66 Pages) MICROCHIP

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MCP8021/2

DS20006265D-page 22

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4.2

Bias Generator

The internal bias generator controls several voltage

rails. Two fixed output Low Dropout linear regulators,

internal bias supply LDOs and a charge pump are

controlled through the bias generator. In addition, the

bias generator performs supervisory functions.

4.2.1

CHARGE PUMP

An unregulated charge pump is utilized to boost the

input to the VBOOT voltage regulator during low input

supply voltage conditions. When the input bias to the

device (VDD) drops below the CPSTART voltage, the

charge pump is activated. When activated, 2 x VDD is

presented to the input of the VBOOT regulator. The

charge pump is capable of maintaining a VBOOT output

of +9V @ 15 mA for a VDD supply voltage of 5.25V to 7V.

The charge pump is capable of maintaining a VBOOT

output of +12V @ 20 mA for a supply input voltage of 7V

to 13.5V. The charge pump is disabled and bypassed at

VDD voltages above 13.5V, allowing an output voltage of

+12V @ 30 mA.

The typical Charge Pump Flying Capacitor, CCP, is a

0.1 µF to 1.0 µF ceramic capacitor.

4.2.2

VBOOT VOLTAGE REGULATOR

The VBOOT voltage regulator rail is used to supply bias

voltage for the integrated 3-phase power MOSFET

bridge drivers.

The regulator is capable of supplying 30 mA of

external load current. The regulator has a minimum

overcurrent limit of 40 mA.

The regulator gets its power from the integrated

charge pump. When operating at supply voltages

(VDD) that are above +14V, the integrated charge

pump will be disabled and the VDD supply will power

the VBOOT voltage regulator. The VBOOT regulator out-

put may be lower than the designed voltage, while

operating in the VDD range of +12.5V to +13.0V, due to

the dropout voltage of the regulator.

The VBOOT regulator requires an output capacitor,

connected from VBOOT to GND, to stabilize the internal

control loop and to sustain the bootstrap capacitor

energy. A minimum of 4.7 µF ceramic output capaci-

tance is required for the VBOOT voltage regulator

output; 10 µF is recommended when switching large

MOSFET gate loads. The output capacitor forces a

time delay between setting the OE pin high (to transi-

tion from Standby mode to Active mode) and the

VBOOT regulator voltage output rising above the volt-

age required to set an internal VBootReady flag. The

PWM inputs must not be activated while the VBOOT

output is charging the output capacitors to the

VBootReady voltage (typically 6.0V). The time

required before allowing the PWM inputs to become

active, after setting OE high to transition from Standby

mode to Active mode, is dependent on output capaci-

tance, any extra loads and supply voltage ramp-up

time. The user should allow a minimum time of

0.94 ms for the VBOOT output voltage to rise above the

VBootReady voltage. A voltage of 6V and supply cur-

rent of 30 mA may be used for this delay estimation.

See Equation 4-1.

EQUATION 4-1:

OE PIN HIGH TO VBOOT

READY

There is a time-out function that allows the state

machine to move from VBOOT to active after 15 ms,

regardless of the VBOOT ready voltage. This time-out

function prevents the driver from hanging up if the

VBOOT voltage is overloaded.

There is also a capacitive voltage divider formed by the

three bootstrap capacitors and the VBOOT capacitor.

The VBOOT capacitor should be selected so that when

the VBOOT supply is active and the bootstrap capacitors

are charged, the voltage at the bootstrap capacitors will

be greater than the driver undervoltage shutdown volt-

age, 4.5V. For a system with VBOOT = 12V, VMIN = 4.5V

and N = 3 x 1 µF CBOOTSTRAP capacitors charging at

the same time, the desired CVBOOT capacitor is 1.8 µF

(see Equation 4-2). Since the VBOOT supply requires a

4.7 µF capacitor, a 4.7 µF capacitor should be used.

The initial voltage seen by the bootstrap capacitors

using a 4.7 µF VBOOT capacitor will be 7.32V. See

Equation 4-3.

EQUATION 4-2:

VBOOT CAPACITOR

EQUATION 4-3:

BOOTSTRAP VOLTAGE

The VBOOT output is disabled when the driver

transitions to Standby or Sleep mode.

Table 4-4 shows the Faults that will also disable the

VBOOT voltage regulator.

dt = (C

 dV)/(I)

dt = (4.7 µF

 6V)/(30 mA)

dt = 0.94 ms

 CBOOTSTRAP)

(VBOOT)  (VMIN) – 1

CVBOOT =

VBOOTSTRAP =

(VBOOT  CVBOOT)

((CVBOOT + N  CBOOTSTRAP)

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