PM7346 datasheet(87/419 Pages) PMC

87 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 66

Bit-oriented codes (BOCs) are received on the FEAC channel as 16-bit

sequences each consisting of 8 ones, a zero, 6 code bits, and a trailing zero

("111111110xxxxxx0"). BOCs are validated when repeated at least 10 times.

The RBOC can be enabled to declare a code valid if it has been observed for 8

out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the RBOC

Configuration/Interrupt Enable Register. The RBOC declares that the code is

removed if two code sequences containing code values different from the

detected code are received in a moving window of ten code periods.

Valid BOCs are indicated through the RBOC Interrupt Status Register. The BOC

bits are set to all ones ("111111") when no valid code is detected. The RBOC

can be programmed to generate an interrupt when a detected code has been

validated and when the code is removed.

9.6

RDLC Facility Data Link Receiver

The RDLC is a microprocessor peripheral used to receive LAPD/HDLC frames

on any serial HDLC bit stream that provides data and clock information such as

the DS3 C-bit parity Path Maintenance Data Link, the E3 G.832 Network

Requirement byte or the General Purpose data link (selectable using the

RNETOP bit in the S/UNI-QJET Data Link and FERF/RAI Control register), the

E3 G.751 Network Use bit, or the J2 m-bit Data Link.

The RDLC detects the change from flag characters to the first byte of data,

removes stuffed zeros on the incoming data stream, receives packet data, and

calculates the CRC-CCITT frame check sequence (FCS).

In the address matching mode, only those packets whose first data byte matches

one of two programmable bytes or the universal address (all ones) are stored in

the FIFO. The two least significant bits of the address comparison can be

masked for LAPD SAPI matching.

Received data is placed into a 128-level FIFO buffer. An interrupt is generated

when a programmable number of bytes are stored in the FIFO buffer. Other

sources of interrupt are detection of the terminating flag sequence, abort

sequence, or FIFO buffer overrun.

The Status Register contains bits which indicate the overrun or empty FIFO

status, the interrupt status, and the occurrence of first flag or end of message

bytes written into the FIFO. The Status Register also indicates the abort, flag,

and end of message status of the data just read from the FIFO. On end of

message, the Status Register indicates the FCS status and if the packet

contained a non-integer number of bytes.

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