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P4C164L-100P6ILF Folha de dados(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C164L-100P6ILF Folha de dados(HTML) 1 Page - Pyramid Semiconductor Corporation |
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1 / 11 page ![]() 1 Document # SRAM116 REV B Revised June 2007 V CC Current (Commercial/Industrial) — Operating: 55 mA — CMOS Standby: 3 µA Access Times —80/100 (Commercial or Industrial) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE 1, CE2 and OE OE OE OE OE Inputs Memory locations are specified on address pins A 0 to A 12. Reading is accomplished by device selection (CE 1 low CE 2 high) and output enabling (OE) while write en- able ( WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE 1 or OE is HIGH or WE or CE2 is LOW. Package options for the P4C164L include 28-pin 300 and 600 mil DIP and 28-pin 330 mil SOP packages. P4C164L LOW POWER 8K x 8 STATIC CMOS RAM Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —28-Pin 300 and 600 mil DIP —28-Pin 330 mil SOP FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DESCRIPTION The P4C164L device provides asynchronous operation with matching access and cycle times. FEATURES The P4C164L is a 64K density low power CMOS static RAM organized as 8Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 80 ns and 100 ns are available. CMOS is utilized to reduce power consumption to a low level. DIP (P5, P6), SOP (S5) TOP VIEW |
Nº de peça semelhante - P4C164L-100P6ILF |
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Descrição semelhante - P4C164L-100P6ILF |
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