DSPIC30F6010 datasheet(80/203 Pages) MICROCHIP

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dsPIC30F2010

DS70118G-page 78

13.7

QEI Module Operation During CPU

Idle Mode

Since the QEI module can function as a quadrature

encoder interface, or as a 16-bit timer, the following

section describes operation of the module in both

modes.

13.7.1

QEI OPERATION DURING CPU IDLE

MODE

When the CPU is placed in the Idle mode, the QEI

module will operate if the QEISIDL bit (QEICON<13>)

= 0. This bit defaults to a logic ‘0’ upon executing POR

and BOR. For halting the QEI module during the CPU

Idle mode, QEISIDL should be set to ‘1’.

13.7.2

TIMER OPERATION DURING CPU

IDLE MODE

When the CPU is placed in the Idle mode and the QEI

module is configured in the 16-bit Timer mode, the

16-bit

timer

will

operate

the

QEISIDL

bit

(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon

executing POR and BOR. For halting the timer module

during the CPU Idle mode, QEISIDL should be set

to ‘1’.

If the QEISIDL bit is cleared, the timer will function

normally, as if the CPU Idle mode had not been

entered.

13.8

Quadrature Encoder Interface

Interrupts

The quadrature encoder interface has the ability to

generate an interrupt on occurrence of the following

events:

• Interrupt on 16-bit up/down position counter

rollover/underflow

• Detection of qualified index pulse, or if CNTERR

bit is set

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI interrupt flag bit, QEIIF, is asserted upon

occurrence of any of the above events. The QEIIF bit

must be cleared in software. QEIIF is located in the

IFS2 status register.

Enabling an interrupt is accomplished via the respec-

tive enable bit, QEIIE. The QEIIE bit is located in the

IEC2 Control register.

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