MCP6231 datasheet(8/28 Pages) MICROCHIP

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MCP6231/2/4

DS21881C-page 8

4.0

APPLICATION INFORMATION

The MCP6231/2/4 family of op amps is manufactured

using Microchip’s state-of-the-art CMOS process and

is specifically designed for low-cost, low-power and

general-purpose applications. The low supply voltage,

low quiescent current and wide bandwidth makes the

MCP6231/2/4 ideal for battery-powered applications.

4.1

Rail-to-Rail Inputs

The MCP6231/2/4 op amps are designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 4-1 shows the input voltage exceeding

the supply voltage without any phase reversal.

FIGURE 4-1:

The MCP6231/2/4 Show No

Phase Reversal.

The input stage of the MCP6231/2/4 op amps use two

differential input stages in parallel. One operates at low

common mode input voltage (VCM) and the other at

high VCM. With this topology, the device operates with

VCM up to 300 mV above VDD and 300 mV below VSS.

The

input

offset

voltage

measured

VCM =VSS – 300 mV and VDD + 300 mV to ensure

proper operation.

Input voltages that exceed the input voltage range

(VSS – 0.3V to VDD + 0.3V at 25°C) can cause

excessive current to flow into or out of the input pins.

Current beyond ±2 mA can cause reliability problems.

Applications that exceed this rating must be externally

limited with a resistor, as shown in Figure 4-2.

FIGURE 4-2:

Input Current-Limiting

Resistor (RIN).

4.2

Rail-to-Rail Output

The output voltage range of the MCP6231/2/4 op amps

is VDD – 35 mV (max.) and VSS + 35 mV (min.) when

RL =10kΩ is connected to VDD/2 and VDD = 5.5V.

Refer to Figure 2-14 for more information.

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity-gain buffer (G = +1) is the most

sensitive to capacitive loads, but all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series resis-

tor at the output (RISO in Figure 4-3) improves the feed-

back loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The band-

width will be generally lower than the bandwidth with no

capacitive load.

FIGURE 4-3:

Output resistor, RISO

stabilizes large capacitive loads.

Figure 4-4 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

signal gain are equal. For inverting gains, GN is

1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

Time (1 ms/div)

OUT

VIN

DD = 5.0V

G = +2 V/V

Minimum expected V

()

–

2 mA

----------------------------------------------------------------------------

≥

Maximum expected V

() V

–

2 mA

-------------------------------------------------------------------------------

≥

VIN

RIN

VOUT

MCP623X

–

VIN

RISO

VOUT

MCP623X

–

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