PS700 datasheet(9/38 Pages) MICROCHIP

9 / 38 page

 2004 Microchip Technology Inc.

DS21760F-page 9

PS700

3.2.3

SAMPLE-SLEEP MODE

In Sample-Sleep mode, the PS700 goes into the Sleep

state and wakes up at user-programmed intervals to

perform a set of conversions as programmed for the

A/D cycle. The purpose of Sample-Sleep is to achieve

the minimum power consumption possible while

periodically measuring specified parameters.

While the PS700 is in the Sleep portion of Sample-

Sleep interval, all of the analog circuitry is shut off. The

Sleep interval time is driven by an independent low-

power on-chip RC oscillator that is separate from the

primary oscillator. The Sleep oscillator consumes much

less power than the primary oscillator, but is less

accurate. While in Sample-Sleep mode, the device

consumes average current in the range of 20

µA.

During the active portion of Sample-Sleep mode, a

single set of conversions is performed and a Run mode

current in the range of 85

µA will be consumed for the

duration of the measurements.

Sample-Sleep mode is invoked by one of the following

actions:

Cell voltage on VC1 or VC2 drops below the trip

point programmed in the VCtrip register with the

corresponding “VC1ent” or “VC2ent” bit set in

the TRIPctrl register. This action can be used to

prevent excessive battery discharge in the event

of a dangerously low cell voltage. Be aware that

Sample-Sleep will not be entered if the “lex” bit

is set, enabling wake-up based on charge

current and the measured current is above the

threshold set in the I+trip register.

Setting the SSLP bit in the OpMode register.

The host can take this action when the system is

entering a low-power standby condition and it is

desired to periodically measure and accumulate

current, voltage, or temperature.

Current less than the I-trip register value when

“Ient” bit is set in the TRIPctrl register.

The Sample-Sleep interval is determined by the

programming of the “Sampdiv” bits within the A/D Con-

figuration register, together with the “SSLPdiv” bits

within the OpMode register. The sample interval is

2**(Sampdiv) * 2**(SSLPdiv) * 0.5 sec. The possible

Sample-Sleep interval time, therefore, ranges from a

minimum of 0.5 sec to over 136 minutes.

Exit from Sample-Sleep mode to Run mode can be

accomplished by clearing the “SSLP” bit or by program-

ming a wake-up based on pack voltage or current.

Wake-up based on charge current will occur when the

“Iex” bit is set in the TRIPctrl register and the charging

current value is above the threshold programmed in the

I+trip register. Wake-up based on pack voltage will

occur when the “VPex” bit is set in the TRIPctrl register

and the pack voltage rises above the threshold

programmed in the SStrip register.

3.2.4

SHELF-SLEEP MODE

Shelf-Sleep mode is the lowest power mode and is

intended to preserve battery capacity when the battery

pack is shipped or stored or if the battery voltage drops

below a specified threshold. While in Shelf-Sleep

mode, no measurements occur, no accumulation is

performed

and

SMBus

communications

are

recognized. In addition, volatile memory is not

maintained.

Entry to Shelf-Sleep mode is enabled by programming

the “SHent” bit = 1 or if VPACK is less than VPtrip. The

Shelf-Sleep mode will then be entered when the

SMBus pins (both SDA and SCL) drop from a high to a

low level for a minimum time period specified by tSHELF.

This action will also occur if the battery pack is

physically disconnected from the system.

Exit from the Shelf-Sleep mode back to Run mode will

occur when the SMBus pins (both SDA and SCL) are

both pulled from a low to high condition and remain

high for a minimum time of tWAKE, signifying system

activity or the connection of the pack to the host.

3.3

General Purpose Input/Outputs

The NTC and VC2 pins have alternate functions of

general purpose I/O; IO0 and IO1, respectively. These

pins can be configured as digital general purpose

inputs/outputs if their normal application functions of

temperature and cell monitoring are not needed. Their

configuration is controlled in the GPIOctrl register.

The IO0 (NTC) pin may be configured as a push-pull

output, an open-drain driver with internal pull-up, or as

a tri-stated pin. When configured as a push-pull or

open-drain output, the output high voltage is the 3.0V

internally regulated supply. When the output function is

disabled, an external circuit may drive the pin as an

input with a voltage range of 0-3.0V. The input function

may be used whether or not the pin is driven by the

PS700. In addition, the input function may be disabled,

in which case the input buffer is powered down,

preventing current drain if the NTC pin rests at an

intermediate level.

The IO1 (VC2) pin is similar to that of NTC except it is

an open-drain output only. IO1 has no explicit output

enable control; therefore, if the output is set to a logic

‘1’, the internal pull-down is turned off which tri-states

the pin. The input function is the same as IO0.

Note:

If the IO0 and/or IO1 pins are being used

for their analog functions, their respective

GPIO output and input functions must be

disabled. The GPIO function may be

totally disabled by clearing the appropriate

GPIOctrl bit.

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