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SCC68692 Folha de dados(PDF) 21 Page - NXP Semiconductors |
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SCC68692 Folha de dados(HTML) 21 Page - NXP Semiconductors |
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21 / 30 page ![]() Philips Semiconductors Product specification SCC68692 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 21 X1/CLK A1–A4 RWN CSN D0–D7 DTACKN tCSC tAS tRWS tDH tDAT tDAH tRWH tCSW tDS tCSD tDCW tAH NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. SD00148 Figure 5. Bus Timing (Write Cycle) X1/CLK INTRN IACKN D0–D7 DTACKN tCSC tDD tDF tCSD tDAL tDCR tDAH tDAT NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. SD00149 Figure 6. Interrupt Cycle Timing |
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