MPC8280CVRM datasheet(19/80 Pages) FREESCALE

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MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

AC Electrical Characteristics

6.2 SIU AC Characteristics

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the MPC8280 should not exceed +/– 150 psec of jitter

(peak-to-peak). This represents total input jitter—the combination of short term

(cycle-to-cycle) and long term (cumulative). The duty cycle of CLKIN should not

exceed the ratio of 40:60. The rise/file time of CLKIN should adhere to the typical

SDRAM device AC clock requirement of 1 V/ns to meet SDRAM AC specs.

NOTE: Spread Spectrum Clocking

Spread spectrum clocking is allowed with 1% input frequency down-spread at

maximum 60 KHz modulation rate regardless of input frequency.

NOTE: PCI AC Timing

The MPC8280 meets the timing requirements of PCI Specification Revision 2.2.

Refer to Sections 7.2 and 7.3 and “Note: Tval (Output Hold)” to determine if a

specific clock configuration is compliant.

Table 11 lists SIU input characteristics.

Table 11. AC Characteristics for SIU Inputs 1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

Spec Number

Characteristic

Value (ns)

Setup

Hold

Setup

Hold

66 MHz

83 MHz 100 MHz 66 MHz

83 MHz 100 MHz

sp11

sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/

TEA

3.50.5

0.50.5

sp12

sp10 Data bus in normal mode

3.5

0.5

sp13

sp10 Data bus in ECC and PARITY modes

3.5

0.5

sp13a

sp10 Pipeline mode—Data bus (with or

without ECC/PARITY)

2.5

0.5

sp14

sp10 DP pins

3.5

0.5

sp14a

sp10 Pipeline mode—DP pins

—

2.5

—

0.5

sp15

sp10 All other pins

3.5

0.5

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