MC9328MX1DVM15 datasheet(5/100 Pages) FREESCALE

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Signals and Connections

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

SDIBA [3:0]

SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These

signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.

MA [11:10]

SDRAM address signals

MA [9:0]

SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on

SDRAM cycles.

DQM [3:0]

SDRAM data enable

CSD0

SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable

by programming the system control register.

CSD1

SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by

programming the system control register. By default, CSD1 is selected, so it can be used as boot

chip-select by properly configuring BOOT [3:0] input pins.

RAS

SDRAM Row Address Select signal

CAS

SDRAM Column Address Select signal

SDWE

SDRAM Write Enable signal

SDCKE0

SDRAM Clock Enable 0

SDCKE1

SDRAM Clock Enable 1

SDCLK

SDRAM Clock

RESET_SF

Not Used

Clocks and Resets

EXTAL16M

Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut

down.

XTAL16M

Crystal output

EXTAL32K

32 kHz crystal input

XTAL32K

32 kHz crystal output

CLKO

Clock Out signal selected from internal clock signals.

RESET_IN

Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all

modules (except the reset module and the clock control module) are reset.

RESET_OUT

Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the

following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

POR

Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally

generated by an external RC circuit designed to detect a power-up event.

JTAG

TRST

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

TDO

Serial Output for test instructions and data. Changes on the falling edge of TCK.

TDI

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

TCK

Test Clock to synchronize test logic and control register access through the JTAG port.

TMS

Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of

TCK.

Table 2. i.MX1 Signal Descriptions (Continued)

Signal Name

Function/Notes

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