PLUS153DA datasheet(6/8 Pages) PHILIPS

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Philips Semiconductors Programmable Logic Devices

Product specification

PLUS153B/D

Programmable logic arrays

(18

× 42 × 10)

October 22, 1993

LOGIC PROGRAMMING

The PLUS153B/D is fully supported by

industry standard (JEDEC compatible) PLD

CAD tools, including Philips Semiconductors

SNAP design software package. ABEL

™ and

CUPL

™ design software packages also

support the PLUS153B/D architecture.

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic

capture format.

PLUS153B/D logic designs can also be

generated using the program table entry

format, which is detailed on the following

page. This program table entry format is

supported by SNAP only.

To implement the desired logic functions, the

state of each logic variable from logic

equations (I, B, O, P, etc.) is assigned a

symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc.,

are defined below.

PROGRAMMING AND

SOFTWARE SUPPORT

Refer to Section 9

(Development Software)

and Section 10

(Third-Party

Programmer/Software Support) of this data

handbook for additional information.

AND ARRAY – (I, B)

CODE

STATE

INACTIVE1, 2

CODE

STATE

CODE

STATE

CODE

STATE

I, B

–

P, D

I, B

P, D

I, B

P, D

I, B

P, D

I, B

DON’T CARE

OR ARRAY – (B)

VIRGIN STATE

A factory shipped virgin device contains all

fusible links intact, such that:

1. All outputs are at “H” polarity.

2. All Pn terms are disabled.

3. All Pn terms are active on all outputs.

NOTES:

1. This is the initial unprogrammed state of all links.

2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either

I or B) are left intact.

ABEL is a trademark of Data I/O Corp.

CUPL is a trademark of Logical Devices, Inc.

CODE

ACTIVE LEVEL

LOW

(INVERTING)

CODE

ACTIVE LEVEL

HIGH1

(NON–INVERTING)

OUTPUT POLARITY – (B)

CODE

INACTIVE

CODE

Pn STATUS

ACTIVE1

•

Pn STATUS

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