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Os motores de busca de Datasheet de Componentes eletrônicos |
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TVP7002PZP Folha de dados(PDF) 21 Page - Texas Instruments |
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TVP7002PZP Folha de dados(HTML) 21 Page - Texas Instruments |
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21 / 52 page  www.ti.com Timing RGBin HSYNC DATACLK RGBout D0 D1 D3 D4 D5 P0 P1 P3 ... P10 P11 P12 HSOUT Programmable Width NPD clocks latency HSOUT Programmable Start 4:4:4 RGB/YCbCr Output Timing. Npd = 18 clock cycles. HSOUT start is programmable in register 21h. RGBin HSYNC DATACLK Gout Y0 Y1 Y3 Y4 Y5 P0 P1 P3 ... P10 P11 P12 HSOUT Programmable Width NPD clocks latency U0 V1 U2 V3 U4 Bout HSOUT Programmable Start 4:2:2 YCbCr Output Timing. Npd = 39 clock cycles. HSOUT start is programmable in register 21h. TVP7002 SLES206 – MAY 2007 The TVP7002 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing diagrams are shown for operation with internal PLL clock at phase 0 and HSOUT Output Start = 0. For the 4:2:2 mode, CbCr data output is on the BOUT[9:0] output port. Figure 6. Output Timing Diagram 21 Submit Documentation Feedback |
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