AD9516-4SLASHPCBZ datasheet(11/84 Pages) AD

11 / 84 page

AD9516-4

Rev. 0 | Page 11 of 84

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not

include PLL and VCO; uses rising edge

of clock signal

CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1

fS rms

BW = 12 kHz to 20 MHz

CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4

fS rms

BW = 12 kHz to 20 MHz

CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16

215

fS rms

Calculated from SNR of ADC method.

DCC not used for even divides

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5

245

fS rms

Calculated from SNR of ADC method.

DCC on

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not

include PLL and VCO; uses rising edge

of clock signal

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; VCO Divider Not Used

fS rms

BW = 12 kHz to 20 MHz

CLK = 1 GHz; LVDS = 200 MHz; Divider = 5

113

fS rms

BW = 12 kHz to 20 MHz

CLK = 1.6 GHz; LVDS= 100 MHz; Divider = 16

280

fS rms

Calculated from SNR of ADC method.

DCC not used for even divides

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not

include PLL and VCO; uses rising edge

of clock signal

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16

365

fS rms

Calculated from SNR of ADC method.

DCC not used for even divides

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210

fS rms

Calculated from SNR of ADC method

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

285

fS rms

Calculated from SNR of ADC method

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

350

fS rms

Calculated from SNR of ADC method

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