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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 25

Figure 32:

4LS Pipeline Overview

Regarding the output mode, it is possible to select between two different modes: 12-bit and 8-bit

serialization. It is also possible to select between different readout modes: 1-To-1, 2-To-1 and 4-To-1,

which allows output multiplexing.

7.2

Startup Sequence

During power up or power down, no signal on any pin shall exceed VDDIO by more than 0.3 V (except

for VDDA).

The VDDxx must never be allowed to exceed the VDDA supply by more than 0.5 V during power-up.

Therefore, the VDDA supply should always be higher than the lower voltage supply.

The main clock (MCLK) shall remain low for at least 1 µs after all powers have reached their final

values.

The global reset for the PLL, N_RST_PLL, shall remain low for at least 1 µs after MCLK had started.

The global reset for the logic, N_RST_LOGIC, shall remain low for at least 10 µs after the reset of the

PLL was released.

Figure 33 shows an example for the power on sequence where the times to be guarded are present.

Reset

CVC

Reset

CDS

Integration I

Reset

CVC

Reset

CDS

Integration I+1

Reset

CVC

Reset

CDS

Integration I+2

Conversion I

Conversion I+1

Sample

St art AD

St art

Readout

Readout I

Scan I (4 Lines)

Scan I+1 (4 Lines)

Scan I+2 (4 Lines)

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