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AM62A7 Folha de dados(PDF) 82 Page - Texas Instruments

Nome de Peças AM62A7
Descrição Electrónicos  AM62Ax Sitara™ Processors
PDF  238 Pages
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7.5 Operating Performance Points
Table 7-1 defines the maximum operating frequency of the clocks for each device speed grade and Table 7-2
defines the only valid Operating Performance Points (OPPs) for the device subsystem and core clocks.
Table 7-1. Device Speed Grades
Speed
Grade
VDD_CORE
(V)(1)
MAXIMUM OPERATING FREQUENCY (MHz)
MAXIMUM
TRANSITION
RATE (MT/s)
(2)
A53SS
(Cortex-
A53x)
C7x
MAIN
SYSCLK
MCU
R5F
/
SYSCLK
DEVICE
MANAGER
R5F
/
CLK
HSM
VPAC
VENC
/
VDEC
MJPEG
LPDDR4
M
0.75/0.85
800
500
500
800
/
400
800
/
400
400
375
400
250
3200
N
0.75
800
850
500
800
/
400
800
/
400
400
375
400
250
3200
0.85
1000
O
0.75/0.85
1000
500
500
800
/
400
800
/
400
400
375
400
250
3200
P
0.75/0.85
1000
500
500
800
/
400
800
/
400
400
375
400
250
3733
Q
0.75
1000
850
500
800
/
400
800
/
400
400
375
400
250
3200
0.85
1000
R
0.75
1000
850
500
800
/
400
800
/
400
400
375
400
250
3733
0.85
1000
S
0.75
1250
500
500
800
/
400
800
/
400
400
375
400
250
3200
0.85
1400
T
0.75
1250
500
500
800
/
400
800
/
400
400
375
400
250
3733
0.85
1400
U
0.75
1250
850
500
800
/
400
800
/
400
400
375
400
250
3200
0.85
1400
1000
V
0.75
1250
850
500
800
/
400
800
/
400
400
375
400
250
3733
0.85
1400
1000
(1)
Nominal operating voltage, see Recommended Operating Conditions.
(2)
Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.
AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77A – MARCH 2023 – REVISED AUGUST 2023
www.ti.com
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Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1



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