AM62A7 datasheet(148/238 Pages) TI1

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[i]

GPMC_A[MSB:1]

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADCn_ALE

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

Address 0

Address 1

Valid

Data Upper

FA9

FA10

FA3

FA9

FA3

FA13

FA1

FA4

FA12

FA10

FA0

FA16

FA0

FA10

FA5

GPMC_07

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock

edge. FA5 value must be stored inside AccessTime register bits field.

GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-52. GPMC and NOR Flash — Asynchronous Read — 32–Bit

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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