S32K310 datasheet(80/143 Pages) NXP

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1. These specs will have degraded performance when used in extended supply voltage operation range, i.e. normal supply

voltage range specification is exceeded.

2. Required ADC sampling time specified by parameter AN_TADCSA needs to be used at the ADC conversion to guarantee

the specified accuracy. A smaller sampling time leads to a less accurate result.

3. If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise.

10.3 Low Power Comparator (LPCMP)

Table 37. Low Power Comparator (LPCMP)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

idda(IDHSS)

vdda Supply

Current, High Speed

Mode 1,2

—

240

—

idda(IDLSS)

vdda Supply

Current, Low Speed

Mode 1,2

—

idda(IDHSS)

vdda Supply

Current, high speed

mode, DAC only 2

—

idda_lkg

vdda Supply

Current, module

disabled 2

—

vdda=5.5V, T=25C

—

TDHSB

Propagation Delay,

High Speed Mode 3

—

200

—

TDLSB

Propagation Delay,

Low Speed mode 3

—

TDHSS

Propagation Delay,

High Speed Mode 4

—

400

—

TDLSS

Propagation Delay,

Low Speed mode 4

—

TIDHS

Initialization Delay,

High Speed Mode 5

—

TIDLS

Initialization Delay,

Low Speed mode 5

—

VAIO

Analog Input Offset

Voltage, High Speed

Mode

-25

+/-1

—

VAIO

Analog Input Offset

Voltage, Low Speed

mode

-40

+ /- 5

—

VAHYST0

Analog Comparator

Hysteresis, High

Speed Mode

—

HYSTCTR[1:0]= 2'b00 —

Table continues on the next page...

NXP Semiconductors

Analog modules

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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