PCK2000MDB datasheet(8/12 Pages) PHILIPS

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Philips Semiconductors

Product specification

PCK2000M

CK97 (66/100MHz) Mobile System Clock Generator

1998 Sep 29

ALL CLOCK OUTPUTS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

Tamb = 0°C to +70°C

UNIT

NOTES

MIN

MAX

TPZL, TPZH

Output enable time

1.0

8.0

TPLZ, TPHZ

Output disable time

1.0

8.0

NOTES:

1. See Figure 3 for measure points.

2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.

3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.

4. The CPUCLK must always lead the PCICLK as shown in Figure 2.

5. THKH is measured @ 2.0V as shown in Figure 4.

6. THKL is measured @ 0.4V as shown in Figure 4.

7. The time is specified from when VDDQ achieves its nominal operating level (typical condition is VDDQ = 3.3V) until the frequency output is

stable and operating within specification.

8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.

9. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification.

10. THRISE and THFALL (REF, PCI) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V

AC WAVEFORMS

VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3

VX = VOL + 0.3V

VY = VOH –0.3V

VOL and VOH are the typical output voltage drop that occur with the

output load.

CPUCLK

1.25V

SW00240

1.25V

CPUCLK

VDDQ2

VSS

VDDQ2

VSS

THSKW

Figure 1. CPUCLK to CPUCLK skew

CPUCLK

1.5V

1.25V

PCICLK

VDDQ2

VSS

VDDQ3

VSS

THPOFFSET

SW00241

Figure 2. CPUCLK to PCICLK offset

SW00242

THKP

DUTY CYCLE

THKH

TRISE

TFALL

THKL

TPKP

TPKH

TRISE

TFALL

TPKL

2.5V CLOCKING

INTERFACE

3.3V CLOCKING

INTERFACE

(TTL)

2.0

1.25

0.4

2.4

1.5

0.4

Figure 3. 2.5V/3.3V Clock waveforms

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