PCK2000DL datasheet(3/14 Pages) PHILIPS

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Philips Semiconductors

Product specification

PCK2000

CK97 (66/100MHz) System Clock Generator

1998 Sep 29

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

1, 2, 47

REF [0–2]

14.318 MHz clock outputs

VSSREF

GROUND for REF outputs

VDDREF

POWER for REF outputs

XTAL_IN

14.318 MHz crystal input

XTAL_OUT

14.318 MHz crystal output

6, 12, 18

VSSPCI [0–2]

GROUND for PCI outputs

PCICLK_F

Free-running PCI output

9, 15

VDDPCI [0–1]

POWER for PCI outputs

8, 10, 11, 13, 14, 16, 17

PCICLK [1–7]

PCI clock outputs.

19, 33

VDDCORE [0–1]

Isolated POWER for core

20, 32

VSSCORE [0–1]

Isolated GROUND for core

VDD 48MHz

POWER for 48MHz outputs

VSS 48MHz

GROUND for 48MHz outputs

22, 23

48MHz [0–1]

48MHz outputs

26, 27

SEL0,1

Logic select pins.

SEL100/66

Select pin for enabling 66 MHz or 100MHz. L = 66 MHz

H = 100MHz

PWRDWN

Control pin to put device in powerdown state, active low

CPUSTOP

Control pin to disable CPU clocks, active low

PCISTOP

Control pin to disable PCI clocks, active low

37, 41

VDDCPU [0–1]

POWER for CPU outputs

34, 38

VSSCPU [0–1]

GROUND for CPU outputs

35, 36, 39, 40

CPUCLK [0–3]

CPU clock outputs @2.5V

VSSAPIC

GROUND for IOAPIC outputs

VDDAPIC

POWER for IOAPIC outputs

44, 45

IOAPIC [0–1]

IOAPIC output @ 2.5V

28, 42

RESERVED

Reserved for future use

NOTES:

1. VDD and VSS names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on

the performance of the device. In reality, the platform will be configured with the VDDAPIC and VDDCPU pins tied to a 2.5V supply, all

remaining VDD pins tied to a common 3.3V supply and all VSS pins being common.

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