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IMX7DCEC Folha de dados(PDF) 97 Page - NXP Semiconductors

Nome de Peças IMX7DCEC
Descrição Electrónicos  i.MX 7Dual Family of Applications Processors Datasheet
PDF  161 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX7DCEC Folha de dados(HTML) 97 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023
NXP Semiconductors
97
(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
Figure 61. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Figure 62. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
Table 74. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
CSI_VSYNC to CSI_HSYNC time
tV2H
33.5
—
ns
P2
CSI_HSYNC setup time
tHsu
1
—
ns
P3
CSI DATA setup time
tDsu
1
—
ns
CSI_PIXCLK
CSI_VSYNC
CSI_DATA[15:00]
P5
P1
P3
P4
CSI_HSYNC
P2
P6
P7
CSI_PIXCLK
CSI_VSYNC
CSI_DATA[15:00]
P6
P1
P3
P4
CSI_HSYNC
P2
P5
P7



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