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AM29BDD160G Folha de dados(PDF) 77 Page - Advanced Micro Devices

Nome de Peças AM29BDD160G
Descrição Electrónicos  16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
PDF  79 Pages
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Fabricante Electrônico  AMD [Advanced Micro Devices]
Página de início  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDD160G Folha de dados(HTML) 77 Page - Advanced Micro Devices

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June 7, 2006
Am29BDD160G
75
REVISION SUMMARY
Revision B (September 30, 2002)
Initial public release.
Revision B+1 (October 7, 2002)
Distinctive Characteristics
Changed maximum power consumption on burst
mode read, program/erase operations, and standby
mode.
Burst Mode Read table
Changed t
CES specification from 7, 8, and 9 ns to 4, 5,
and 6 ns, respectively.
DC Characteristics table
Deleted I
CC2 specification. Changed ICCB OE# test
condition from V
IH to VIL. Added 1 MHz test condition
to I
CC1; changed OE# test condition from VIH to VIL.
Changed I
CC3 and ICC4 maximum values and added
typical values. Changed maximum values for I
CC5,
I
CC7, and ICC8. Added Note 4 to table.
AC Characteristics
Erase and Program Operations table: Replaced TBDs
for t
AH and tWP with values.
Erase and Programming Performance table
Replaced TBDs and existing typical and maximum val-
ues with new values.
Revision B+2 (October 14, 2002)
Distinctive Characteristics, DC Characteristics
Changed V
CC CMOS standby current to 30 mA max.
Absolute Maximum Ratings
Changed maximum rating for V
CC to 3.0 V.
Revision B+3 (November 22, 2002)
Product Selector Guide
Added availability note. Changed minimum initial clock
delay and maximum CE# access time on 54D, 65D,
64C, and 65A speeds. Changed maximum OE# ac-
cess time on 65A and 90A speeds.
Ordering Information
Added availability note.
See Table 8 , Burst Initial Access Delay
Deleted definitions and settings columns and added
initial burst access columns.
Figure 3, Initial Burst Delay Control
Modified drawing: Deleted arrows connecting ad-
dress/data cycles. Deleted setting callouts. Changed
number of delay cycles callouts. Moved start of Valid
Address cycle.
Falling CLK Edge Output and Two-CLK Data Hold
Deleted figure.
See Table 9 , Configuration Register Definitions
Modified descriptions for CR3–CR10.
See Table 16 , CFI Device Geometry Definition
Modified description of data at address 2Ch (x32
mode); added data 0003h.
DC Characteristics
Added maximum ICC6 specification.
AC Characteristics
Asynchronous Read Operations: Changed tCE specifi-
cations for 54D, 65D, 64C, and 65A speed options.
Changed tDF specifications for 65A and 90A speed op-
tions.
Revision B+4 (April 8, 2003)
Distinctive Characteristics
Corrected typo in Single power supply operation.
Corrected typo in Performance characteristics.
Product Selector Guide
Updated Max Burst Access Delay for the 54D, 65D,
64C, and 80C speed options.
Global
Removed references to interleaving operations
throughout datasheet.
Table 6. 16-Bit and 32-Bit Linear and Interleaved
Burst Data Order
Removed 2nd row for “Four Interleaved Data Trans-
fers” and “Eight Interleaved Data Transfers”.
Continuous Burst Read Operations, Figure 3. and
Figure 4. Wait Function During Continuous Burst
Reads at Wordline Boundary, Figure 5. and Figure
6. Odd/Even Starting address Continuous Burst
Mode Alignment
Removed from datasheet.
Table 9. Configuration Register Definitions
Added “Reserved” references to table.
Sector Protection
Added Sector and Sector Group section.



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