CS82C54Z datasheet(21/22 Pages) INTERSIL

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82C54

Ceramic Leadless Chip Carrier Packages (CLCC)

j x 45o

h x 45o

PLANE 2

PLANE 1

0.010

E H

0.010

E F

-E-

0.007

E F

S HS

-H-

-F-

J28.A MIL-STD-1835 CQCC1-N28 (C-4)

28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.060

0.100

1.52

2.54

6, 7

0.050

0.088

1.27

2.23

----

0.022

0.028

0.56

0.71

2, 4

0.072 REF

1.83 REF

0.006

0.022

0.15

0.56

0.442

0.460

11.23

11.68

0.300 BSC

7.62 BSC

0.150 BSC

3.81 BSC

0.460

11.68

0.442

0.460

11.23

11.68

0.300 BSC

7.62 BSC

0.150 BSC

3.81 BSC

0.460

11.68

0.050 BSC

1.27 BSC

0.015

0.38

0.040 REF

1.02 REF

0.020 REF

0.51 REF

0.045

0.055

1.14

1.40

0.045

0.055

1.14

1.40

0.075

0.095

1.90

2.41

0.003

0.015

0.08

0.038

N28

Rev. 0 5/18/94

NOTES:

1. Metallized castellations shall be connected to plane 1 terminals

and extend toward plane 2 across at least two layers of ceramic

or completely across all of the ceramic layers to make electrical

connection with the optional plane 2 terminals.

2. Unless otherwise specified, a minimum clearance of 0.015 inch

(0.38mm) shall be maintained between all metallized features

(e.g., lid, castellations, terminals, thermal pads, etc.)

3. Symbol “N” is the maximum number of terminals. Symbols “ND”

and “NE” are the number of terminals along the sides of length

“D” and “E”, respectively.

4. The required plane 1 terminals and optional plane 2 terminals (if

used) shall be electrically connected.

5. The corner shape (square, notch, radius, etc.) may vary at the

manufacturer’s option, from that shown on the drawing.

6. Chip carriers shall be constructed of a minimum of two ceramic

layers.

7. Dimension “A” controls the overall package thickness. The maxi-

mum “A” dimension is package height before being solder dipped.

8. Dimensioning and tolerancing per ANSI Y14.5M-1982.

9. Controlling dimension: INCH.

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