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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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TDA935X Folha de dados(PDF) 13 Page - NXP Semiconductors |
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TDA935X Folha de dados(HTML) 13 Page - NXP Semiconductors |
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13 / 118 page  2001 Jan 18 13 Philips Semiconductors Tentative Device Specification TV signal processor-Teletext decoder with embedded µ-Controller TDA935X/6X/8X PS/N2 series 92H R/W TP2H TP2H<15> TP2H<14> TP2H<13> TP2H<12> TP2H<11> TP2H<10> TP2H<9> TP2H<8> 93H R/W TP2PR TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0> 94H R/W TP2CRL ------ TP2CRL<1> TP2CRL<0> 96H R/W P0CFGA Reserved P0CFGA<6> P0CFGA<5> Reserved Reserved Reserved Reserved Reserved 97H R/W P0CFGB Reserved P0CFGB<6> P0CFGB<5> Reserved Reserved Reserved Reserved Reserved 98H R/W SADB - - - DC_COMP SAD<3> SAD<2> SAD<1> SAD<0> 9CH R TP2CL TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0> 9DH R TP2CH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0> 9EH R/W P1CFGA P1CFGA<7> P1CFGA<6> Reserved Reserved P1CFGA<3> P1CFGA<2> P1CFGA<1> P1CFGA<0> 9FH R/W P1CFGB P1CFGB<7> P1CFGB<6> Reserved Reserved P1CFGB<3> P1CFGB<2> P1CFGB<1> P1CFGB<0> A0H R/W P2 Reserved ------ P2<0> A6H R/W P2CFGA Reserved P2CFGA<6> P2CFGA<5> P2CFGA<4> P2CFGA<3> P2CFGA<2> P2CFGA<1> P2CFGA<0> A7H R/W P2CFGB Reserved P2CFGB<6> P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0> A8H R/W IE EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 B0H R/W P3 Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0> B2H R/W TXT18 NOT<3> NOT<2> NOT<1> NOT<0> 0 0 BS<1> BS<0> B3H R/W TXT19 TEN TC<2> TC<1> TC<0> 0 0 TS<1> TS<0> B4H R/W TXT20 DRCS ENABLE OSD PLANES 0 0 OSD LANG ENABLE OSD LAN<2> OSD LAN<1> OSD LAN<0> B5H R/W TXT21 DISP LINE<1> DISP LINES<0> CHAR SIZE<1> CHAR SIZE<0> Reserved CC ON I2C PORT0 CC/TXT B6H R TXT22 GPF1<7> GPF1<6> GPF1<5> GPF1<4> GPF1<3> GPF1<2> GPF1<1> GPF1<0> B7H R/W CCLIN 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0> B8H R/W IP 0 PBUSY PES2 PCC PT1 PX1 PT0 PX0 B9H R/W TXT17 0 FORCE ACQ<1> FORCE ACQ<0> FORCE DISP<1> FORCE DISP<0> SCREEN COL<2> SCREEN COL<1> SCREEN COL<0> BAH R WSS1 0 0 0 WSS<3:0> ERROR WSS<3> WSS<2> WSS<1> WSS<0> BBH R WSS2 0 0 0 WSS<7:4> ERROR WSS<7> WSS<6> WSS<5> WSS<4> BCH R WSS3 WSS<13:11> ERROR WSS<13> WSS<12> WSS<11> WSS<10:8> ERROR WSS<10> WSS<9> WSS<8> BEH R/W P3CFGA Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0> BFH R/W P3CFGB Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0> C0H R/W TXT0 X24 POSN DISPLAY X24 AUTO FRAME DISABLE HEADER ROLL DISPLAY STATUS ROW ONLY DISABLE FRAME VPS ON INV ON ADD R/W Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Table 2 SFR Map |
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