CC1110-RTR1 datasheet(54/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 54 of 202

IP1 (0xB9) – Interrupt Priority 1

Bit

Name

Reset

R/W

Description

7:6

R/W

Not used.

IP1_5

R/W

Interrupt group 5, priority control bit 1, refer to Table 30

IP1_4

R/W

Interrupt group 4, priority control bit 1, refer to Table 30

IP1_3

R/W

Interrupt group 3, priority control bit 1, refer to Table 30

IP1_2

R/W

Interrupt group 2, priority control bit 1, refer to Table 30

IP1_1

R/W

Interrupt group 1, priority control bit 1, refer to Table 30

IP1_0

R/W

Interrupt group 0, priority control bit 1, refer to Table 30

IP0 (0xA9) – Interrupt Priority 0

Bit

Name

Reset

R/W

Description

7:6

R/W

Not used.

IP0_5

R/W

Interrupt group 5, priority control bit 0, refer to Table 30

IP0_4

R/W

Interrupt group 4, priority control bit 0, refer to Table 30

IP0_3

R/W

Interrupt group 3, priority control bit 0, refer to Table 30

IP0_2

R/W

Interrupt group 2, priority control bit 0, refer to Table 30

IP0_1

R/W

Interrupt group 1, priority control bit 0, refer to Table 30

IP0_0

R/W

Interrupt group 0, priority control bit 0, refer to Table 30

IP1_x

IP0_x

Priority Level

0 – lowest

3 – highest

Table 30: Priority Level Setting

Group

Interrupts

IP0

RFTXRX

DMA

IP1

ADC

IP2

URX0

UTX0

IP3

URX1

UTX1

IP4

ENC

P1INT

IP5

WDT

P0INT

Table 31: Interrupt Priority Groups

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