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SY100S336

Micrel, Inc.

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Pin

Function

CP

Clock Pulse Input

CEP

Count Enable Parallel Input (Active LOW)

Serial Data Input/Count Enable Trickle

Input (Active LOW)

Select Inputs

MR

Master Reset Input

Preset Inputs

Serial Data Input

TC

Terminal Count Output

Data Outputs

Complementary Data Outputs

PIN NAMES

SY100S336

4-STAGE COUNTER/

SHIFT REGISTER

s Max. shift frequency of 700MHz

s Clock to Q delay max. of 1100ps

s Internal 75K

s Industry standard 100K ECL levels

s Extended supply voltage option:

s Voltage and temperature compensation for improved

noise immunity

s 50% faster than Fairchild 300K at lower power

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

FEATURES

DESCRIPTION

The SY100S336 functions either as a modulo-16 up/

down counter or as a 4-bit bidirectional shift register and is

designed for use in high-performance ECL systems. Three

Select inputs (Sn) are provided for determining the mode of

operation. The Function Table lists the available modes of

operation. In order to allow cascading for multistage

counters, two Count Enable controls (CEP, CET) are

provided. The CET input also functions as the Serial Data

as the Serial Data input for the shift-down operation.

When the device is in the counting mode, the Terminal

Count (TC) goes to a logical LOW when the count reaches

15 for count-up or reaches 0 for count-down. When in the

CET input allows these signals to be interconnected from

one stage to the next higher stage for multistage counting

initialization of the counter by entering data in parallel to

preset the counter. A logic HIGH on the Master Reset (MR)

overrides all other inputs and asynchronously clears the

flip-flops. An additional synchronous Clear is provided, as

well as a complement function which synchronously inverts

the contents of the flip-flops. All inputs have 75K

Ω pull-

down resistors.

Rev.: H

Amendment: /0

Issue Date:

March 2006