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AT89C51CC03U-RDTIM Folha de dados(PDF) 21 Page - ATMEL Corporation

Nome de Peças AT89C51CC03U-RDTIM
Descrição Electrónicos  Enhanced 8-bit MCU with CAN Controller and Flash Memory
PDF  197 Pages
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Fabricante Electrônico  ATMEL [ATMEL Corporation]
Página de início  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT89C51CC03U-RDTIM Folha de dados(HTML) 21 Page - ATMEL Corporation

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AT89C51CC03
4182K–CAN–05/06
Registers
Table 2. CKCON0 Register
CKCON0 (S:8Fh)
Clock Control Register
Note:
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Reset Value = 0000 0000b
76
54
32
1
0
CANX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7CANX2
CAN clock
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
6WDX2
WatchDog clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5
PCAX2
Programmable Counter Array clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4SIX2
Enhanced UART clock (MODE 0 and 2)
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3T2X2
Timer2 clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer1 clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
1T0X2
Timer0 clock
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
0X2
CPU clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select 6 clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2"bits.



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