AT89C5132-ROTIL datasheet(27/38 Pages) ATMEL

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AT89C5132

4173CS–USB–07/04

Two-wire Interface

Timings

Table 1. TWI Interface AC Timing

DD = 2.7 to 3.3 V, TA = -40 to +85°C

Notes:

1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of

100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-up

resistor, this must be < 1

µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered

out. Maximum capacitance on bus-lines SDA and

SCL= 400 pF.

4. TCLCL= T

OSC= one oscillator clock period.

Waveforms

Figure 9. Two Wire Waveforms

Symbol

Parameter

INPUT

Min

Max

OUTPUT

Min

Max

THD; STA

Start condition hold time

14·TCLCL

(4)

4.0

µs(1)

TLOW

SCL low time

16·TCLCL

(4)

4.7

µs(1)

THIGH

SCL high time

14·TCLCL

(4)

4.0

µs(1)

TRC

SCL rise time

µs-(2)

TFC

SCL fall time

0.3

µs0.3 µs(3)

TSU; DAT1

Data set-up time

250 ns

20·TCLCL

(4)- TRD

TSU; DAT2

SDA set-up time (before repeated START condition)

250 ns

µs(1)

TSU; DAT3

SDA set-up time (before STOP condition)

250 ns

8·TCLCL

(4)

THD; DAT

Data hold time

0 ns

8·TCLCL

(4) - TFC

TSU; STA

Repeated START set-up time

14·TCLCL

(4)

4.7

µs(1)

TSU; STO

STOP condition set-up time

14·TCLCL

(4)

4.0

µs(1)

TBUF

Bus free time

14·TCLCL

(4)

4.7

µs(1)

TRD

SDA rise time

µs

(2)

TFD

SDA fall time

0.3

µs0.3 µs(3)

Tsu;DAT1

su;STA

Tsu;DAT2

hd;STA

high

low

SDA

(INPUT/OUTPUT)

0.3 VDD

0.7 V

buf

Tsu;STO

0.7 VDD

0.3 V

Trd

SCL

(INPUT/OUTPUT)

hd;DAT

su;DAT3

START or Repeated START condition

START condition

STOP condition

Repeated START condition

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