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WM8785GEDS/V Folha de dados(PDF) 18 Page - Wolfson Microelectronics plc

Nome de Peças WM8785GEDS/V
Descrição Electrónicos  24-Bit, 192kHz Stereo ADC
PDF  31 Pages
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Fabricante Electrônico  WOLFSON [Wolfson Microelectronics plc]
Página de início  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8785GEDS/V Folha de dados(HTML) 18 Page - Wolfson Microelectronics plc

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WM8785
Production Data
w
PD Rev 4.1 December 2006
18
In DSP/PCM mode, the left channel MSB is available on either the 1
st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 21 and Figure
22. In device slave mode, Figure 23 and Figure 24, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.
Figure 21 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
Figure 22 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)



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