WM8591GEDSSLASHRV datasheet(23/51 Pages) WOLFSON

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Production Data

WM8591

PD Rev 4.0 December 2005

The transfer of data is complete when there is a low to high transition on DI while CL is high. After

receiving a complete address and data sequence the WM8591 returns to the idle state and waits for

another start condition. If a start or stop condition is detected out of sequence at any point during

data transfer (i.e. DI changes while CL is high), the device jumps to the idle condition.

Figure 19 2-wire Serial Interface

B[15:9] are Control Address Bits

B[8:0] are Control Data Bits

The WM8591 has two possible device addresses, which can be selected using the CE pin.

CE STATE

DEVICE ADDRESS

Low

0011010 (0 x 34h)

High

0011011 (0 x 36h)

Table 10 2-Wire MPU Interface Address Selection

CONTROL INTERFACE REGISTERS

DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

0001010

DAC Interface Control

1:0

DACFMT

[1:0]

R11 (0Bh)

0001011

ADC Interface Control

1:0

ADCFMT

[1:0]

Interface format Select

00 : right justified mode

01: left justified mode

10: I

2S mode

11: DSP mode A or B (selected

by DACLRP and ADCLRP)

In left justified, right justified or I

2S modes, the LRP register bit controls the polarity of

ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the

opposite of that shown Figure 12, Figure 13, etc. Note that if this feature is used as a means of

swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes,

the LRP register bit is used to select between early and late modes.

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

0001010

DAC Interface Control

DACLRP

R11 (0Bh)

0001011

ADC Interface Control

ADCLRP

In left/right/ I

2S modes:

ADCLRC/DACLRC Polarity (normal)

0 : normal ADCLRC/DACLRC

polarity

1: inverted ADCLRC/DACLRC

polarity

In DSP mode:

0 : DSP mode A

1: DSP mode B

By default, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and

DACBCLK

and should ideally change on the falling edge. Data sources that change

ADCLRC/DACLRC and DIN on the rising edge of ADCBCLK/DACBCLK can be supported by setting

the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in

Figure 12, Figure 13, etc.

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