May 4, 2020

CONFIDENTIAL INFORMATION Rev. 1.2

SABRE9006A Datasheet

7

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

FUNCTIONAL DESCRIPTION

NOTATATIONS for Sampling Rates

Mode

fs

DSD

DATA_CLK/64

Serial (PCM) Normal Mode

DATA_CLK/64

SPDIF

SPDIF Sampling Rate

PCM, SPDIF and DSD Pin Connections

The following tables show how the pins are used for PCM and DSD audio formats.

PCM Audio Format

Note: XI clock (MCLK) must be > 192 x fs when using PCM input (normal mode)

Pin Name

Description

DATA1

Frame clock

DATA[2:5]

8-channel PCM serial data

DATA_CLK

Bit clock for PCM audio format

Table 2

SPDIF Audio Formant

Note: XI clock (MCLK) must be > 386 x fs when using SPDIF input

Pin Name

Description

DATA1

SPDIF input

Table 3

DSD Audio Format

Note: XI clock (MCLK) must be > 192 x fs when using DSD input

Pin Name

Description

DATA[1:8]

8-channel DSD data input

DATA_CLK

Bit clock for DSD data input

Table 4

Feature Description

Soft Mute

When Mute is asserted the output signal will ramp to the

–

 level. When Mute is reset the attenuation level will ramp back up

to the previous level set by the volume control register. Asserting Mute will not change the value of the volume control

register. The total time is 8192/(2<Register#16[2:0]>x fs) seconds, where fs = DATA_CLK/64 in PCM serial or DSD modes, or

SPDIF sampling rate in SPDIF mode.