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IP101G-DS-R01 Folha de dados(PDF) 59 Page - List of Unclassifed Manufacturers |
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IP101G-DS-R01 Folha de dados(HTML) 59 Page - List of Unclassifed Manufacturers |
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59 / 65 page ![]() IP101G Data Sheet 7.4.2 MII Timing a. Transmit Timing Requirements Table 15 MII Transmit Timing Requirements Symbol Description Min. Typ. Max. Unit TTclk1 Period of transmit clock output in 100M mode - 40 - ns TTclk1 Period of transmit clock output in 10M mode - 400 - ns Ts1 TXEN, TXD to TX_CLK setup time 10 - - ns Th1 TXEN, TXD to TX_CLK hold time 0 - - ns Figure 19 MII Transmit Timing Requirements b. Receive Timing Table 16 MII Receive Timing Specifications Symbol Description Min. Typ. Max. Unit TRclk1 Period of receive clock output in 100M mode - 40 - ns TRclk1 Period of receive clock output in 10M mode - 400 - ns 20 22 26 ns Td1 1 100Mbps Td1 10Mbps MII_RXCLK rising edge to RXDV, RXD output delay 200 202 206 ns Figure 20 MII Receive Timing Specifications 1 Timing was measured for the pin load TXEN and TXD[3:0] of IP101G. The reference 25MHz clock was from output pin RXCLK of IP101G via the default driving current. 59/65 January 14, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 |
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