DSP56004ROM datasheet(59/82 Pages) FREESCALE

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Specifications

Serial Host Interface (SHI) I2C Protocol Timing

MOTOROLA

DSP56004/D, Rev. 3

2-35

189 First SCL Edge

to HREQ In Not

Asserted (HREQ

In Hold Time)

master

0—0—

—

Note:

CL is in pF, RP is in kΩ, and result is in ns.

A tI2CCP of 34 × TC (the maximum permitted for the given bus load) was used for the calculations in the

Bypassed Filter mode.

A tI2CCP of 36 × TC (the maximum permitted for the given bus load) was used for the calculations in the

Narrow Filter mode.

A tI2CCP of 40 × TC (the maximum permitted for the given bus load) was used for the calculations in the Wide

Filter mode.

A tI2CCP of 43 × TC (the maximum permitted for the given bus load) was used for the calculations in the

Bypassed Filter mode.

A tI2CCP of 46 × TC (the maximum permitted for the given bus load) was used for the calculations in the

Narrow Filter mode.

A tI2CCP of 51 × TC (the maximum permitted for the given bus load) was used for the calculations in the Wide

Filter mode.

A tI2CCP of 52 × TC (the maximum permitted for the given bus load) was used for the calculations in the

Bypassed Filter mode.

A tI2CCP of 56 × TC (the maximum permitted for the given bus load) was used for the calculations in the

Narrow Filter mode.

A tI2CCP of 62 × TC (the maximum permitted for the given bus load) was used for the calculations in the Wide

Filter mode.

Refer to the DSP56004 User’s Manual for a detailed description of how to use the filtering modes.

Figure 2-21 I2C Timing

Table 2-15

SHI Improved I2C Protocol Timing (Continued)

Improved I2C (CL = 50 pF, RP = 2 kΩ)

No.

Char.

Sym.

Mode

Filter

Mode

Expression

50 MHz2

66 MHz3

81 MHz4

Min Max Min Max Min Max

Start

SCL

HREQ

SDA

ACK

MSB

LSB

Stop

171

Stop

173

176

175

177

178

180

179

172

186

182

183

189

174

188

184

187

AA0275

Freescale Semiconductor, Inc.

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