Si5350B-B

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Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021

6.3.4. Output Enable (OEB_0, OEB_1, OEB_2)

Up to three output enable pins (OEB_0/1/2) are available on the Si5350B. Each OEB pin can be linked to any of

the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3, and CLK5; OEB_1 is

linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and CLK5. Any other

combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin forcing a disable

state will be dominant. Clock outputs are enabled when the OEB pin is held low.

The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading

edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its

full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is

configurable as disabled high, disabled low, or disabled in high-impedance.

Figure 9. Example Configuration of a Pin-Controlled Output Enable

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

OEB_0

OEB_1

OEB_0

0

1

CLK Enabled

CLK Disabled

Output State

OEB_2

OEB_1

0

1

CLK Enabled

CLK Disabled

Output State

OEB_2

0

1

CLK Enabled

CLK Disabled

Output State

Clock continues until

cycle is complete

CLKx

OEBx

Clock starts on the

first leading edge

Glitchless Output Enable

Customizable OEB Control

OEB

OEB

OEB

OEB

OEB

OEB

OEB

OEB