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ST7FL19F1MATRE Folha de dados(PDF) 58 Page - STMicroelectronics

Nome de Peças ST7FL19F1MATRE
Descrição Electrónicos  8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
PDF  138 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7FL19F1MATRE Folha de dados(HTML) 58 Page - STMicroelectronics

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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)
11.2.3.4 Output Compare Mode
To use this function, load a 12-bit value in the
Preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the
value stored in the Active DCRxH and DCRxL reg-
isters, the CMPFx bit in the PWMxCSR register is
set and an interrupt request is generated if the
CMPIE bit is set.
In Single Timer mode the output compare function
is performed only on CNTR1. The difference be-
tween both the modes is that in Single Timer
mode, CNTR1 can be compared with any of the
four DCR registers, and in Dual Timer mode,
CNTR1 is compared with DCR0 or DCR1 and
CNTR2 is compared with DCR2 or DCR3. In ROM
devices, the CNTR2 counter is not used for this
comparison.
Notes:
1. The output compare function is only available
for DCRx values other than 0 (reset value).
2. Duty cycle registers are buffered internally. The
CPU writes in Preload Duty Cycle Registers and
these values are transferred to Active Duty Cycle
Registers after an overflow event if the corre-
sponding transfer bit (TRANx bit) is set. Output
compare is done by comparing these active DCRx
values with the counters.
Figure 39. Block Diagram of Output Compare Mode (Single Timer)
DCRx
OUTPUT COMPARE CIRCUIT
COUNTER 1
(ATCSR)
CMPIE
PRELOAD DUTY CYCLE REG0/1/2/3
ACTIVE DUTY CYCLE REGx
CNTR1
TRAN1
(ATCSR2)
OVF
(ATCSR)
CMPFx (PWMxCSR)
CMP
REQUEST
INTERRUPT
1



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